Chip bugs with the Intel Core 2 Duo processors

[reck]

I've got a E6600, first i've heard about this.

The Core 2 Memory management unit (MMU) does not operate as previously specified or implemented in previous generations of x86 hardware. This may cause problems, many of them serious security and stability issues, with existing operating system software. Intel's documentation states that their programming manuals will be updated "in the coming months" with information on recommended methods of managing the Translation Lookaside Buffer (TLB) for Core 2 to avoid issues, and admits that, "in rare instances, improper TLB invalidation may result in unpredictable system behavior, such as hangs or incorrect data."

Among the issues noted:

Write-protect or non-execute bit for a page table entry is ignored.
Floating point instruction non-coherencies.
Allowed memory corruptions outside of the range of permitted writing for a process by running common instruction sequences.
Intel errata AI65, AI79, AI43, AI39, AI90, AI99 are said to be particularly serious.

Among those who have noted the errata to be particularly serious are OpenBSD's Theo de Raadt[1] and DragonFly BSD's Matthew Dillon.

But Linus Torvalds said the following so maybe it's not so bad.

Linus Torvalds called the issue "totally insignificant", adding, "The biggest problem is that Intel should just have documented the TLB behavior better.

[old_blaggard]

I've been running on a Core 2 Duo Intel processor since July, and I have not had any problems with it.  That's interesting though - I wonder if the "Floating point instruction non-coherencies" would create differences between scenes rendered on a machine with a new processor and a machine with an old one.

[cyphyr]

I think your right OB, I remember "back in the day" seeing inconsistencies between intel and amd output on lightwave procedural renders.
Richard